In regard to a microprocessor, it is common that a cache memory is incorporated therein for the purpose of increasing its memory access performance. However, the cache memory is suitable for handling an instruction or data, which is frequently accessed, but not so effective for data which is made unnecessary once it has been used. While a large volume of temporary data like this is often handled in the applications such as image processing or voice processing, trying using a cache memory to access these data will drive out data more suitable for the cache memory, which should be normally cached therein, because of the finite capacity of the cache memory, reducing the efficiency as a whole. Therefore, it is desired in order to these data at a high speed to have an internal memory in addition to the cache memory.
In the case where a cache memory is used, the average access performance from a CPU (Central Processing Unit) can be improved, but the cache memory changes in hit/miss depending on its access history until then, which makes difficult to predict the execution time. Therefore, the cache memory can be not appropriate for precise real time control in some cases. In an application such as real time control, it is desired to store a memory information (an instruction or data) in not a cache memory but a permanent internal memory.
In the case where a microprocessor has an internal memory according to the forementioned standpoint instead of or in addition to the cache memory, it is important to increase the speed and efficiency of the data transfer between the internal memory and external memory.
According to the consideration of the inventor, transfer control by a DMAC (direct memory access controller) is conducted in block transfer and the CPU in the middle of a transfer operation is able to carry out another process, which offers a good transfer efficiency. However, it has been shown that such transfer control requires to synchronize the action of the DMAC with the process by the CPU (in settings of a data transfer condition, and startup and termination waits) and as such, the overhead owing to the synchronization is made remarkable especially when a transferred volume is small. Also, in the case where a block transfer instruction is used, when the period of time during which the CPU is occupied by the transfer process is prolonged, the overhead is made longer as in the case of using a DMAC. If such block transfer instruction is dedicated, it becomes easy to optimize the process, but there may be the following case: a new instruction code cannot be added, or the addition of a new instruction code poses a disadvantage.
The following document has been found from the patent search, which was made after the invention was completed. In JP-A-2000-231550, it is described that a microcomputer having a load/store instruction executing unit capable of executing a load/store instruction is provided with a RAM (Random Access Memory) which data can be read out from and written in by the load/store instruction executing unit and which allows DMA (Direct Memory Access) transfer between RAM and an external memory. The forementioned Patent Gazette says that a dedicated block transfer instruction or the like may be used to access a RAM used for a special application other than cache instead of the load/store instruction (in the paragraph No. 76). However, there is no disclosure about the operation according to the block transfer instruction.